Virtual Memory — Demand Paging & CPU Execution

Program chopped into pages → stored on disk → loaded into RAM on demand → executed by CPU. 3 physical frames + 4 program pages = page faults and FIFO replacement.

Speed: Step 0 | Hits: 0 Faults: 0 | Evictions: 0

CPU

Program Counter

page 0, offset 0

— press Step to begin —

Disk (Swap / Backing Store) all 4 program pages

Page on disk Being read Already loaded

Physical Memory (RAM) 3 frames — limited!

Just loaded Being evicted Accessed

Page Table

Page	Valid	Frame

        Valid bit = ✓ means page is in RAM.

        ✗ means page is still on disk → page fault!

        Replacement policy: FIFO

Execution Log

Key concepts illustrated

Demand paging — pages are only loaded from disk into RAM when first touched.
Page fault — CPU accesses a page whose valid bit is 0 → OS loads it from disk.
Page table — per-process map from virtual page → physical frame (+ valid bit).
Page replacement (FIFO) — when RAM is full, the oldest-loaded page is evicted to disk.
Instruction fetch + data access — both go through the MMU, both can fault independently.