Logical → Physical Address Translation

A paging-based virtual memory demonstration for OS Main Memory Management
Page Size8 bytes
Logical Space32 bytes (4 pages)
Physical Memory64 bytes (8 frames)
Address Bits5 = 2 (page) + 3 (offset)
(0–31) Speed:
1. Logical Address
→
2. Page Table Lookup
→
3. Physical Address
Waiting for translation…

Program (Logical View)

Program sees contiguous logical addresses 0–31
Page boundaries Current address

Page Table

OS maps each logical page to a physical frame
Page #Frame #Valid
Lookup: frame = PageTable[page]

Physical Memory (RAM)

8 frames × 8 bytes = 64 bytes total
Frame number Translated byte

How paging works

A logical (virtual) address generated by the CPU is split into two parts: the high-order bits form a page number (p), and the low-order bits form an offset (d) within the page. The MMU uses p as an index into the page table to find the corresponding frame number (f) in physical memory. The physical address is then f × page_size + d, or equivalently the bits of f concatenated with d. This lets the OS place the logically-contiguous pages into any free frames in RAM — they do not need to be adjacent.